New Design for HLFF and iP-DCO Flip-Flop Suitable for High-Performance and Low-Power VLSI Applications
نویسنده
چکیده
New designs for Hybrid latch flip-flip (HLFF) and implicit-pulsed data-close-to-output (ip-DCO) flipflop circuits are proposed to improve the redundant switching activity, speed and power as these flip-flop circuits are basic building blocks of many timing elements. This paper evaluates and compares the performance of various flip-flop circuits which can reduce the effect of redundant switching activities and glitches. The performance of the various flip-flop circuits based on TSMC 0.18 m process models in the entire range of the supply voltage starting from 0.9V to 1.8V is evaluated by the comparison of the simulation results obtained from HSPICE.The Simulation results reveal that the proposed circuit exhibit better switching activity and is more power efficient and faster when compared with best available flip-flop circuits in the literature. New proposed flip-flop circuits of HLFF and ip-DCOFF have an improvement of 15% and 24% in PDP as well as 16% and 25% in EDP respectively.
منابع مشابه
A new low power high reliability flip-flop robust against process variations
Low scaling technology makes a significant reduction in dimension and supply voltage, and lead to new challenges about power consumption such as increasing nodes sensitivity over radiation-induced soft errors in VLSI circuits. In this area, different design methods have been proposed to low power flip-flops and various research studies have been done to reach a suitable hardened flip-flops. In ...
متن کاملOptimization Of Power For Sequential Elements In Pulse Triggered Flip-Flop Using Low Power Topologies
The choice of flip-flop technologies is an essential importance in design of VLSI integrated circuits for high speed and high performance CMOS circuits. The main objective of this project is to design a Low-Power Pulse-Triggered flip-flop. Flip-flops are the major storage elements in all SOC’s of digital design. They accommodate most of the power that has been applied to the chip. Flip-flop is ...
متن کاملIJSRD - International Journal for Scientific Research & Development| Vol. 3, Issue 09, 2015 | ISSN (online): 2321-0613
The timing elements and clock interconnection Networks such as flip-flops and latches, is One of the most power consuming components in modern very large Scale integration (VLSI) system. The area, power and transistor count will compared and designed using several latches and flip flop stages. Flip Flop is a circuit which is used to store state information. Power consumption is one of the main ...
متن کاملHigh-performance and Low-power Clock Branch Sharing Pseudo-NMOS Level Converting Flip-flop
Multi-Supply voltage design using Cluster Voltage Scaling (CVS) is an effective way to reduce power consumption without performance degradation. One of the major issues in this method is performance and power overheads due to insertion of Level Converting Flip-Flops (LCFF) at the interface from low-supply to high-supply clusters to simultaneously perform latching and level conversion. In this p...
متن کاملDesign of Sub Threshold Flip Flop For Ultra Low Power Applications
Abstract: Power consumption is considered as one of the important challenge in modern VLSI design along with area and speed consideration. Flip flop plays very important role in digital systems. In this paper comparative study of four different flip flops which includes pulse triggered as well as conditional technique flip flop such as IP-DCO, MHLFF, CPSFF, and CPFF topologies in sub threshold ...
متن کامل